FPGA Cores

The proliferation of devices involved in communications and their need to stay connected coupled with an even greater need to exchange huge amounts of data require new media for data transfer with much higher throughputs. This is where single fiber optic cables come into play by virtue of being the fastest medium for transferring data. This medium introduces different multiplexing protocols for transferring multiple digital bit streams such as Plesiochronous Digital Hierarchy (PDH) and its successor Synchronous Digital Hierarchy (SDH). In addition, there is also a need for intercepting and demultiplexing frames of these protocols with the goal of data processing or transferring to other levels of the multiplex.

Multi-Purpose PDH Framer IP Core

PDH Framer Core is a general purpose PDH Framer IP core. It supports framing capabilities for a host of protocols like E1, E2, E3, T1, T2, T3 etc. PDH Framer IP core can be integrated with any FPGA/ASIC logic requiring PDH framer capability. The multi-purpose PDH Framer core acts as the memory mapped peripheral to the CPU. It exports a register interface for configurations and status checks.



  • Multi protocol support on a single platform
  • Protocols supported: E1, E2, E3, V.35, T1, T2, T3
  • Generic Design - Adapts to any of the above serial protocols just by change of firmware
  • Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals and is consistent with ITU-T G.706 specifications
  • Frames to popular T1/E1 standards: 
    • T1: SF, ESF, SLC-96, T1DM 
    • E1: PCM-30, G.704, G.706, G.732 
  • Compliant to ITU-T G.742/G.751, E2 / E3 Framing and multiplexing / de-multiplexing standards
  • Supports Frame Structures from 2 bits to 64 Kbytes
  • Programmable Polynomial CRC
  • Multiple Frame Sync Support: e.g. Normal Frame Sync + CRC4 multi-frame-sync in case of E1 
  • Programmable pattern register for configurable synchronization pattern
  • Support for control channel for communication between the two peers on any of the overhead bits


  • High density Internet E1/E2/E3/T1/T2/T3 interfaces for multiplexers, switches, routers, and digital modems. 
  • Frame Relay Switches and Access Devices 
  • Digital Access and Cross-Connect Systems 
  • PDH Add / Drop Multiplexers (ADMs) 

STM1 Framer

STM1 Framer IP core provides a flexible and resource-efficient FPGA IP core. It can be configured as Framer or Deframer or both as required. STM1 Framer IP core can be imported into any user FPGA logic requiring STM1 framer/deframer capability.



  • Detects and aligns to the STM1 Framing Pattern
  • Synchronizes to the STM1 received frames and generates LOS, LOF and OOF alarms. Inserts framing bytes into the transmit STM1 frames
  • Descrambles received STM1 Frames and Scrambles transmit STM1 frames. Scrambling / De-Scrambling can be enabled or disabled
  • Integrates in built SERDES unit
  • Extracts STM1 Payload for use in STM-1 / AU-3 or STM-1 / AU-4 interface applications, operating at serial interface speeds of 155.52 Mbit/s 
  • Provides termination for SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of three AU-3 paths or a single AU-4 path
  • All the SDH transport and path overheads are extracted from the receive stream and are available for processing
  • Interprets or generates the AU pointer bytes (H1, H2, H3), extracts or inserts the synchronous payload envelope(s), and processes or inserts the path overhead
  • Detects B1, B2 and B3 parity errors
  • Supports dual clock domains, facilitating the use of independent system and line clocks
  • Provides microprocessor interface for configuration, control and status information processing


  • Interfacing with Digital / Optical Cross-Connects
  • ADM Aggregate Cards for TDM and Multi-service applications
  • Terminal Multiplexers
  • Interfacing with Tupp Plus, low order TU pointer processing

E1 Framer

E1 Framer core is a VHDL IP core for framing and de-framing serial E1 data at 2048 Kbps. It complies to ITU-T Recommendation G.704 for basic synchronous frame structure and ITU-T Recommendation G.706 for Frame Alignment and Cyclic Redundancy Check (CRC) procedures. The E1 Framer Core can work as a framer or as a deframer.



  • Highly efficient and optimized VHDL IP Core for framing and de-framing serial E1 (2048Kbps) data bit-stream
  • Compliant to G.704 ITU-T Recommendation for Basic Synchronous Frame Structure at 2048 Kbps line rate.
  • Compliant to G.706 ITU-T Recommendation for Frame Alignment and Cyclic Redundancy Check (CRC) procedures related to Basic frame structure at 2048Kbps defined in recommendation G.704.
  • Configurable as a Framer or as a Deframer
  • Detects and reports loss of basic frame alignment, loss of CRC-4 multiframe alignment, CRC errors and remote alarm indication as Deframer,
  • Provision of interworking between equipment with and without a CRC-4 capability
  • Calculates and inserts CRC-4 bits as Framer, if the equipment supports CRC-4 check 
  • Simple I/O port based configuration for reporting status and alarms
  • Fully synchronous design

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